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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
30
3.1.6.6 Jumperless Processor Speed Settings
The Intel
®
Xeon
TM
processor does not utilize jumpers or switches to set the processor frequency.
The BIOS reads the highest ratio register from all processors in the system. If all processors are
the same speed, the Actual Ratio register is programmed with the value read from the High
Ratio register. If all processors do not match, the highest common value between High and Low
Ratio is determined and programmed to all processors. If there is no value that works for all
installed processors, all processors not capable of speeds supported by the Boot Strap
Processor (BSP) are disabled and an error is displayed.
3.1.6.7 Microcode
IA-32 processors have the capability of correcting specific errata through the loading of an Intel
supplied data block, i.e., microcode update. The BIOS is responsible for storing the update in
non-volatile memory and loading it into each processor during POST. The BIOS allows a
number of microcode updates to be stored in the flash, limited by the amount of free space
available. The BIOS supports variable size microcode updates. The BIOS verifies the
signature prior to storing the update in the flash.
3.1.6.8 Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no
user options to modify the cache configuration, size or policies. The largest and highest level
cache detected is reported in the BIOS Setup.
3.1.6.9 Hyper-Threading Technology
Intel
®
Xeon
TM
processors support Hyper-Threading Technology. The BIOS detects processors
that support this feature and enables the feature during POST. The BIOS Setup provides an
option to selectively enable or disable this feature. The default behavior is “Enabled”.
The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure shows only the physical processors installed. It does not
describe the virtual processors because some operating systems are not able to efficiently
utilize the Hyper-Threading Technology.
3.1.6.10 Intel
®
SpeedStep
®
Technology
Intel Xeon processors support the Geyserville3 (GV3) feature of the Intel
®
SpeedStep
®
Technology. This feature changes the processor operating ratio and voltage similar to the
Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature.
The BIOS implements the GV3 feature in conjunction with the TM2 feature.
3.1.6.11 EM64T Technology Support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Intel Extended Memory 64 technology (EM64T) of the Intel Xeon processors. There is no BIOS
setup option to enable or disable this support. The system will be in IA-32 compatibility mode
when booting to an operating system. Operating system specific drivers are then loaded to
enable this capability.
3.1.6.12 Execute Disable Bit support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Execute Disable (NX) bit in the latest Intel Xeon processors. This option can be enabled or
disabled in the BIOS setup utility. It is disabled by default to allow users to opt-in to the
protection this feature provides.