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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
Revision 2.0
9
5.2.12.7 Alert-in-Progress Termination..........................................................................118
5.2.13 NMI Generation ................................................................................................... 118
5.2.14 SMI Generation.................................................................................................... 119
5.3 Platform Management Interconnects...................................................................119
5.3.1 Power Supply Interface Signals...........................................................................119
5.3.1.1 Power-up Sequence.............................................................................................120
5.3.1.2 Power-down Sequence........................................................................................120
5.3.1.3 Power Control Sources .......................................................................................120
5.3.2 System Reset Control..........................................................................................120
5.3.2.1 Reset Signal Output ............................................................................................120
5.3.2.2 Reset Control Sources.........................................................................................121
5.3.3 Temperature-based Fan Speed Control .............................................................. 121
5.3.3.1 Fan Kick Start .....................................................................................................121
5.3.4 Front Panel Control.............................................................................................. 122
5.3.4.1 Power Button ......................................................................................................122
5.3.4.2 Reset Button........................................................................................................122
5.3.4.3 Diagnostic Interrupt Button (Front Panel NMI) .................................................122
5.3.4.4 Chassis ID Button and LED................................................................................123
5.3.4.5 Status/Fault LED.................................................................................................123
5.3.4.6 Chassis Intrusion Switch.....................................................................................124
5.3.4.7 Front Panel Lockout............................................................................................124
5.3.5 Secure Mode Operation....................................................................................... 125
5.3.6 FRU Information ..................................................................................................125
5.3.6.1 mBMC FRU Inventory Area Format..................................................................126
5.4 Sensors................................................................................................................ 126
5.4.1 Sensor Type Codes ............................................................................................. 126
6. Error Reporting and Handling......................................................................................... 132
6.1 Error Logging ....................................................................................................... 132
6.1.1 Error Sources and Types.....................................................................................132
6.1.2 SMI Handler.........................................................................................................132
6.1.2.1 PCI Bus Error......................................................................................................132
6.1.2.2 Processor Bus Error ............................................................................................133
6.1.2.3 Memory Bus Error ..............................................................................................133
6.1.2.4 System Limit Error .............................................................................................133
6.1.2.5 Processor Failure.................................................................................................133
6.1.2.6 Boot Event ..........................................................................................................133
6.1.2.7 Logging Format Conventions .............................................................................133
6.1.3 Single-bit ECC Error Throttling Prevention .......................................................... 134
6.2 Error Messages and Error Codes ........................................................................ 134
6.2.1 POST Error Codes and Messages ...................................................................... 134
6.2.2 Boot Block Error Beep Codes..............................................................................137
6.2.3 POST Error Beep Codes ..................................................................................... 138
6.2.3.1 Troubleshooting BIOS Beep Codes....................................................................138
6.2.4 "POST Error Pause" option .................................................................................138