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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
47
3.6.2 Split Option ROM
The BIOS supports the split option ROM algorithm per the PCI 3.0 specification.
3.6.3 Interrupt Routing
Both the Intel Server Board SE7320SP2 and SE7525GP2 interrupt architectures accommodate
both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O
APICs in the Intel 6300ESB I/O Controller.
3.6.3.1 Legacy Interrupt Routing
For PC-compatible mode, the Intel 6300ESB I/O Controller provides two 82C59-compatible
interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on
level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is
presented to the processors, to which only one processor will respond for servicing. The Intel
6300ESB I/O Controller contains configuration registers that define which interrupt source
logically maps to I/O APIC INTx pins.
Interrupts, both PCI and IRQ types, are handled by the Intel 6300ESB I/O Controller. The Intel
6300ESB I/O Controller then translates these to the APIC bus. The numbers in the table below
indicate the Intel 6300ESB I/O Controller PCI interrupt input pin to which the associated device
interrupt (INTA, INTB, INTC, INTD) is connected. The Intel 6300ESB I/O Controller I/O APIC
exists on the I/O APIC bus with the processors.
Table 9: PCI Interrupt Routing/Sharing
Interrupt INT A INT B INT C INT D
Video PIRQB
Intel 82541 NIC PIRQA
PCI Slot 3 (PCI 32b/33M) PIRQF PIRQD PIRQB PIRQH
PCI Slot 5 (PCI 32b/33M) PIRQE PIRQB PIRQH PIRQD
PCI Slot 2 (64b/66M) PXIRQ1 PXIRQ2 PXIRQ3 PXIRQ0
PCI Slot 1 (64b/66M) PXIRQ0 PXIRQ1
3.6.3.2 APIC Interrupt Routing
For APIC mode, the Intel Server Boards SE7320SP2 and SE7525GP2 interrupt architectures
incorporate three Intel I/O APIC devices to manage and broadcast interrupts to local APICs in
each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI
slots in addition to the ISA compatibility interrupts IRQ(0-15).
When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.
3.6.3.3 Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the Intel
Server Boards SE7320SP2 and SE7525GP2. The actual interrupt map is defined using
configuration registers in the Intel 6300ESB I/O Controller.