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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
36
3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not
consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal
transfers. The Intel 6300ESB I/O Controller IDE system contains two independent IDE signal
channels. They can be electrically isolated independently. They can be configured to the
standard primary and secondary channels (four devices).
3.4.3 SATA Controller
The SATA controller supports two SATA devices providing an interface for SATA hard disks and
ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 Mb/s and Serial ATA
transfers up to 1.5 Gb/s (150 MB/s). The Intel 6300ESB I/O Controller SATA system contains
two independent SATA signal ports. They can be electrically isolated independently. Each
SATA device can have independent timings. They can be configured to the standard primary
and secondary channels.
3.4.4 Low Pin Count (LPC) Interface
The Intel 6300ESB I/O Controller implements an LPC Interface as described in the Low Pin
Count Interface Specification, Revision 1.1. The Low Pin Count (LPC) Bridge function of the
Intel 6300ESB I/O Controller resides in PCI Device 31:Function 0. In addition to the LPC bridge
interface function, D31:F0 contains other functional units including DMA, interrupt controllers,
timers, power management, system management, GPIO, and RTC.
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The Intel 6300ESB I/O Controller supports two types of DMA (LPC and PC/PCI). LPC DMA and
PC/PCI DMA use the Intel 6300ESB I/O Controller DMA controller. The PC/PCI protocol allows
PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PC
REQ#/GNT# pairs. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes
are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit
channels. Channel 4 is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The Intel 6300ESB I/O Controller provides an ISA-compatible Programmable Interrupt
Controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers. The two
interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the Intel 6300ESB I/O Controller supports a serial interrupt scheme. All of the registers
in these modules can be read and restored. This is required to save and restore the system
state after power has been removed and restored to the platform.