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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0
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There are several RASUM (Reliability, Availability, Serviceability, Usability and Manageability)
features built into the Intel E7320 MCH memory interface:
• DIMM sparing allows for one DIMM per channel to be held in reserve and brought on-
line if another DIMM in the channel becomes defective.
• Hardware periodic memory scrubbing, including demand scrub support.
• Retry on uncorrectable memory errors.
• x4 SDDC (Single Device Data Correction) for memory error detection and correction of
any number of bit failures in a single x4 memory device.
3.2.1.3 PCI Express*
The Intel E7320 MCH is part of the first family of Intel chipsets to support the new PCI Express*
high speed serial I/O interface for high I/O bandwidth. The Intel E7320 MCH implementation of
the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev
1.0a. The E7320 MCH provides one configurable x8 PCI Express interface with a maximum
theoretical bandwidth of 4GB/s. The x8 PCI Express interface may alternatively be configured
(bifurcated) as two independent x4 PCI Express interfaces. On the server board SE7320SP2,
the PCI-Express bandwidth is divided between two independent PCI-Express buses; one
operating at x4 for add-in cards, and one embedded on the board for possible future
upgradeability.
The Intel E7320 MCH is a root class component as defined in the PCI Express Interface
Specification, Rev 1.0a. The PCI Express interfaces of the MCH support connection to a variety
of bridges and devices compliant with the same revision of the specification. Refer to the
SE7320SP2/SE7525GP2 Tested Hardware and OS List for the adapters tested on those
systems.
3.2.1.4 Hub Interface
The MCH interfaces with the Intel 6300ESB I/O Controller Hub via a dedicated Hub Interface
supporting a peak bandwidth of 266MB/s using a x4 base clock of 66MHz. The 6300ESB I/O
controller will be discussed in further detail later in this document.
3.3 E7525 Chipset
The architecture of the server board SE7525GP2 is designed around the Intel® E7525 chipset.
The server board SE7320SP2 is designed around the E7320 chipset and was discussed in the
previous section. The Intel E7525 chipset is a subset of the Intel E7520 chipset and consists of
two components which together are responsible for providing the interface between all major
sub-systems found on the server board including the processor, memory, and I/O sub-systems.
These components are the:
• Memory Controller Hub (MCH)
• I/O Controller Hub (Intel 6300ESB)
The following sub-sections will provide an overview describing the primary functions and
supported features of each chipset component. Later sections will discuss how these features
are implemented on the server board SE7525GP2 in greater detail.