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Preliminary Data Sheet, Rev. 5 USS-720
Instant USB
September 1999 USB-to-
IEEE
1284 Bridge
Lucent Technologies Inc. 5-23
13
IEEE
1284 Port (continued)
Interrupts
The USS-720 can return interrupt status on the inter-
rupt pipe. Interrupt status may be generated as a result
of one of seven separately maskable conditions. Any
interrupts that are pending will no longer be pending
after a read operation. The individual conditions are
described in the sections that follow.
nAck Interrupt
The nAck interrupt is enabled by setting the Interrupt
Enable bit in the Control Register. An interrupt will be
generated whenever nAck transitions from 0 to 1. Inter-
rupt status is indicated by the nAck Interrupt bit in the
Extended Control Register.
EPP Time-Out Interrupt
The EPP time-out interrupt is enabled by setting the
EPP Time-Out Interrupt Mask bit in the Control Regis-
ter to 0. Note that this is a change from typical host-
side parallel port hardware, where interrupts on EPP
time-out conditions are enabled by the Interrupt Enable
bit in the Control Register.
An EPP time-out occurs when the peripheral fails to
respond to an EPP handshake within the time allowed
by the
IEEE
1284 specification. If this occurs, there is
no reliable way to determine whether the peripheral is
still functioning or not, or whether the byte in transit was
transferred properly, and it will be up to software to
attempt to recover by resetting the connection or some
other means.
nFault Interrupt
The nFault interrupt is enabled by setting the nFault
Interrupt Mask bit in the USS-720 Control Register to 0.
Interrupt status is reported via the nFault Interrupt bit in
the Extended Control Register. The interrupt is gener-
ated when in ECP Mode and either the nFault line tran-
sitions from 1 to 0 or the nFault line is low and the
interrupt is unmasked. This may indicate that the
peripheral has reverse data to transmit.
Bulk In Interrupt
The Bulk In interrupt is enabled by setting the Bulk In
Interrupt Mask bit in the USS-720 Control Register to 0.
Interrupt status is reported by the Bulk In Interrupt bit in
the Extended Control Register, as well as the Bulk In
Empty bit in the same register. This interrupt is gener-
ated when there is Bulk In data available for reading by
the host. By enabling this interrupt, the host may use
the automatic polling of the interrupt pipe to receive
notification of incoming data, rather than explicitly poll-
ing the Bulk In pipe.
Bulk Out Interrupt
The Bulk Out interrupt is enabled by setting the Bulk
Out Interrupt Mask bit in the USS-720 Control Register
to 0. Bulk Out empty status is reported via the Bulk Out
Empty bit in the Extended Control Register. This inter-
rupt is generated when the Bulk Out data pipeline goes
completely empty. By enabling this interrupt, the host
may use the automatic polling of the interrupt pipe to
be notified of the completion of a data transfer, rather
than explicitly polling the Bulk Out Empty bit.
Change Interrupt
The Change interrupt is enabled by setting the Change
Interrupt Mask bit in the USS-720 Control Register to 0.
There is no Interrupt Status bit associated with the
Change Interrupt. This interrupt is generated when any
of the parallel port signal lines driven by the peripheral
(nAck, Busy, nFault, PError, Select, or PLH) change
state.
Disconnect Interrupt
The Disconnect interrupt is enabled by setting the Dis-
connect Interrupt Mask bit in the USS-720 Control
Register to 0. There is no Interrupt Status bit associ-
ated with the Disconnect interrupt. This interrupt is
generated when the Peripheral Logic High signal
makes a transition from 1 to 0, or when Peripheral
Logic High is 0 and all other parallel port signal lines
driven by the peripheral (nAck, Busy, nFault, PError,
and Select) are high for longer than one second. Either
of these conditions should indicate that the peripheral
has been disconnected from the USS-720.