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MVS-8000SF
1-8. Checks on Completion of Installation
D6103 (A-10) : WASH2 FPGA CONFIG DONE
status LED
WASH2 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6104 (A-9) : WASH1 FPGA CONFIG DONE status
LED
WASH1 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6105 (A-9) : KEYER4 FPGA CONFIG DONE
status LED
KEYER4 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6106 (A-9) : KEYER3 FPGA CONFIG DONE
status LED
KEYER3 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6107 (A-9) : KEYER2 FPGA CONFIG DONE
status LED
KEYER2 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6108 (A-9) : KEYER1 FPGA CONFIG DONE
status LED
KEYER1 FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
D6109 (A-10) : WKG FPGA CONFIG DONE status
LED
WKG FPGA CONFIG DONE status indication.
Not lit when configuration is completed.
<Connector>
CN6000 (A-6) : ISP common connector
Used only for production in the assembly factory. Used for
program writing into the JTAG device with ISP.
<TEST terminal>
E6062 (N-12), E6063 (N-7), E6064 (N-1), E6065 (K-
10), E6066 (K-4), E6069 (E-4), : GND terminal
Use this terminal as the earth point for measuring the
respective check terminals.
TP6000 (P-8) : SYS_CLK signal check terminal
Used for checking the SYSTEM CLOCK signal.
TP6060 (A-2) :
++
++
+3.3 V check terminal
+3.3 V measuring terminal.
TP6061 (A-4), TP6067 (G-1), TP6068 (F-4) :
++
++
+1.8 V
check terminal
+1.8 V measuring terminal.
TP6101 (N-13) : VD (vertical sync) signal check
terminal
Used to check the VD signal supplied from the mother
board.
TP6102 (N-13) : CKX (control timing) signal check
terminal
Used to check the CKX signal supplied from the mother
board.
TP6103 (N-13) : HD (horizontal sync) signal check
terminal
Used to check the HD signal supplied from the mother
board.
TP6104 (N-12) : FLOE (field odd even) signal
check terminal
Used to check the FLOE signal supplied from the mother
board.
TP6800 (N-13) : HALF VIDEO CLOCK signal check
terminal
Used to check the HALF VIDEO CLOCK signal.
TP6801 (N-10) : VCLK (clock for video signal)
signal check terminal
Used to check the clock for video signal
TP6802 (A-11) : DLY_WE terminal
Used to check the Write-Enable signal of the delay circuit.