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4-8 Theory of Operation
4.2.3.1 ALI M1521 (Memory, Cache and DRAM Controller)
The M1521 provides the system controller and data path components for the Extensa
900 Pentium-based system. It provides 64-bit CPU bus interface, 32-bit PCI bus
interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface
including pipeline burst SRAM or asynchronous SRAM, PCI master to DRAM interface,
four PCI master arbiters, and a UMA arbiter. The M1521 bus interfaces are designed
to interface with 3V and 5V buses. It directly connects to 3V CPU bus, 3V or 5V tag,
3V or 5V DRAM bus, and 5V PCI bus.
4.2.3.1.1 Features of the ALI M1521
♦ Supports all Intel/Cyrix
®
/AMD 586-class processors (with host bus of 66 MHz,
60 MHz and 50 MHz at 3V)
♦ Supports M1/K5/Dakota™ CPUs
♦ Supports linear wrap mode for M1
♦ Supports asynchronous/pipeline-burst SRAM
♦ Write-back/dynamic write-back cache policy
♦ Built-in 8K* 2-bit SRAM for MESI protocol to cost and enhance performance
♦ Cacheable memory up to 512 MB with 11-bit tag SRAM
♦ Supports 3V/5V SRAMs for tag address
♦ Supports FPM/EDO/BEDO/SDRAM DRAMs
♦ RAS lines
♦ 64-bit data path to memory
♦ Symmetrical/asymmetrical DRAMs
♦ 3V or 5V DRAMs
♦ Duplicated MA[1:0] driving pins for burst access
♦ No buffer needed for RASJ and CASJ and MA[1:0]
♦ CBR and RAS-only refresh
♦ Supports 64M-bit (16M* 4, 8M* 8, 4M*16) technology DRAMs
♦ Supports programmable-strength MA buffer
♦ Supports error checking and correction (ECC) and parity for DRAM