Filter
Top Products
Peripheral Architecture
www.ti.com
Next, the DDR2 memory controller examines each of the commands selected by the individual masters
and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2 memory controller selects the oldest command.
The DDR2 memory controller may now have a final read and write command. If the Read FIFO is not full,
then the read command will be performed before the write command, otherwise the write command will be
performed first.
Besides commands received from on-chip resources, the DDR2 memory controller also issues refresh
commands. The DDR2 memory controller attempts to delay refresh commands as long as possible to
maximize performance while meeting the SDRAM refresh requirements. As the DDR2 memory controller
issues read, write, and refresh commands to DDR2 SDRAM device, it follows the following priority
scheme:
1. (Highest) Refresh request resulting from the Refresh Must level of urgency (see Section 2.8) being
reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency (see Section 2.8) being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency (see Section 2.8) being reached
6. (Lowest) Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
2.7.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2 memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to
the closed row in the same bank.
To avoid these conditions, the DDR2 memory controller can momentarily raise the priority of the oldest
command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE field
in the Burst Priority Register (BPRIO) sets the number of the transfers that must be made before the
DDR2 memory controller will raise the priority of the oldest command.
26
C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
Submit Documentation Feedback
Copyright © 2005–2011, Texas Instruments Incorporated