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DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDWE
DSDRAS
DSDCAS
DSDDQM0
DSDDQM1
DSDDQS0
DSDDQS1
DBA[2:0]
DEA[13:0]
DED[7:0]
V
REFSSTL
ODT0
DSDDQS0
DSDDQS1
CK
CK
CKE
CS
WE
RAS
CAS
DM
DQS
RDQS
BA[2:0]
A[13:0]
DQ[7:0]
ODT
DQS
RDQS
DDR2
Memory
x8-bit
V
REF
DDR2
Memory
Controller
ODT1
DSDDQGATE0
(A)
DSDDQGATE1
(A)
DSDDQGATE2
(A)
DSDDQGATE3
(A)
DDRSLRATE
DED[15:8]
CK
CK
CKE
CS
WE
RAS
CAS
DM
DQS
RDQS
BA[2:0]
A[13:0]
DQ[7:0]
ODT
DQS
RDQS
DDR2
Memory
x8-bit
V
DD
V
REF
V
REF
Using the DDR2 Memory Controller
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Figure 18. Connecting to Two 8-Bit DDR2 SDRAM Devices
A These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data
manual.
34
C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
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