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DDR2 Memory Controller Registers
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4 DDR2 Memory Controller Registers
Table 17 lists the memory-mapped registers for the DDR2 memory controller. For the memory address of
these registers, see the device-specific data manual.
Table 17. DDR2 Memory Controller Registers
Offset Acronym Register Description Section
00h MIDR Module ID and Revision Register Section 4.1
04h DMCSTAT DDR2 Memory Controller Status Register Section 4.2
08h SDCFG SDRAM Configuration Register Section 4.3
0Ch SDRFC SDRAM Refresh Control Register Section 4.4
10h SDTIM1 SDRAM Timing 1 Register Section 4.5
14h SDTIM2 SDRAM Timing 2 Register Section 4.6
20h BPRIO Burst Priority Register Section 4.7
E4h DMCCTL DDR2 Memory Controller Control Register Section 4.8
38
C6455/C6454 DDR2 Memory Controller SPRU970G–December 2005–Revised June 2011
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