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L1 S1 M1 D1
Data path A
Register file A Register file B
D2
Data path B
S2M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32−bit instruction dispatch
Instruction fetch
SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
Switched central resource
PLL2
L2 memory
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection
1.4IndustryStandard(s)ComplianceStatement
Introduction
Figure1.DDR2MemoryControllerBlockDiagram
TheDDR2memorycontrolleriscompliantwiththeJESD79D-2ADDR2SDRAMstandardwiththe
exceptionoftheOnDieTermination(ODT)feature.TheDSPdoesnotincludeanyon-dieterminating
resistors.Furthermore,theon-dieterminatingresistorsoftheDDR2SDRAMdevicemustbedisabledby
tyingtheODTinputpinoftheDDR2SDRAMmemorytoground.
DSPDDR2MemoryController 10SPRUEK5A–October2007
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