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3.2ConfiguringDDR2MemoryControllerRegisterstoMeetDDR2SDRAMSpecifications
3.2.1ProgrammingtheSDRAMConfigurationRegister(SDCFG)
3.2.2ProgrammingtheSDRAMRefreshControlRegister(SDRFC)
UsingtheDDR2MemoryController
TheDDR2memorycontrollerallowsahighdegreeofprogrammabilityforshapingDDR2accesses.This
providestheDDR2memorycontrollerwiththeflexibilitytointerfacewithavarietyofDDR2devices.By
programmingtheSDRAMConfigurationRegister(SDCFG),SDRAMRefreshControlRegister(SDRFC),
SDRAMTiming1Register(SDTIM1),andSDRAMTiming2Register(SDTIM2),theDDR2memory
controllercanbeconfiguredtomeetthedatasheetspecificationforJESD79D-2AcompliantDDR2
SDRAMdevices.
Asanexample,thefollowingsectionsdescribehowtoconfigureeachoftheseregistersforaccesstotwo
1Gb,16-bitwideDDR2SDRAMdevicesconnectedasshownonFigure17,whereeachdevicehasthe
followingconfiguration:
•Maximumdatarate:533MHz
•Numberofbanks:8
•Pagesize:1024words
•CASlatency:4
ItisassumedthatthefrequencyoftheDDR2memorycontrollerclock(DDR_CLK)issetto266.5MHz.
TheSDRAMconfigurationregister(SDCFG)containsregisterfieldsthatconfiguretheDDR2memory
controllertomatchthedatabuswidth,CASlatency,numberofbanks,andpagesizeoftheattached
DDR2memory.
Table11showstheresultingSDCFGconfiguration.NotethatthevalueoftheTIMUNLOCKfieldis
dependentonwhetherornotitisdesirabletounlockSDTIM1andSDTIM2.TheTIMUNLOCKbitshould
onlybesetto1whentheSDTIM1andSDTIM2needstobeupdated.
Table11.SDCFGConfiguration
FieldValueFunctionSelection
TIMUNLOCKxSetto1tounlocktheSDRAMtimingandtiming2registers.Clearedto0tolocktheSDRAM
timingandtiming2registers.
NM0hToconfiguretheDDR2memorycontrollerfora32-bitdatabuswidth.
CL4hToselectaCASlatencyof4.
IBANK3hToselect8internalDDR2banks.
PAGESIZE2hToselect1024-wordpagesize.
TheSDRAMrefreshcontrolregister(SDRFC)configurestheDDR2memorycontrollertomeettherefresh
requirementsoftheattachedDDR2device.SDRFCalsoallowstheDDR2memorycontrollertoenterand
exitselfrefresh.Inthisexample,weassumethattheDDR2memorycontrollerisnotisinself-refresh
mode.
TheREFRESH_RATEfieldinSDRFCisdefinedastherateatwhichtheattachedDDR2deviceis
refreshedinDDR2cycles.Thevalueofthisfieldmaybecalculatedusingthefollowingequation:
REFRESH_RATE=DDR_CLKfrequency×memoryrefreshperiod
SPRUEK5A–October2007DSPDDR2MemoryController33
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