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REFR
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
2.4.3Activation(ACTV)
ACTV
BANK
ROW
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
PeripheralArchitecture
Figure4.RefreshCommand
TheDDR2memorycontrollerautomaticallyissuestheactivate(ACTV)commandbeforeareadorwriteto
aclosedrowofmemory.TheACTVcommandopensarowofmemory,allowingfutureaccesses(readsor
writes)withminimumlatency.ThevalueofDDR_BA[2:0]selectsthebankandthevalueofA[12:0]selects
therow.WhentheDDR2memorycontrollerissuesanACTVcommand,adelayoft
RCD
isincurredbefore
areadorwritecommandisissued.Figure5showsanexampleofanACTVcommand.Readsorwritesto
thecurrentlyactiverowandbankofmemorycanachievemuchhigherthroughputthanreadsorwritesto
randomareasbecauseeverytimeanewrowisaccessed,theACTVcommandmustbeissuedanda
delayoft
RCD
incurred.
Figure5.ACTVCommand
SPRUEK5A–October2007DSPDDR2MemoryController15
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