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2.4.4Deactivation(DCABandDEAC)
DCAB
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:11, 9:0]
DDR_A[10]
DEAC
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:11, 9:0]
DDR_A[10]
PeripheralArchitecture
Theprechargeallbankscommand(DCAB)isperformedafteraresettotheDDR2memorycontrolleror
followingtheinitializationsequence.DDR2SDRAMsalsorequirethiscyclepriortoarefresh(REFR)and
modesetregistercommands(MRSandEMRS).DuringaDCABcommand,DDR_A[10]isdrivenhighto
ensurethedeactivationofallbanks.Figure6showsthetimingdiagramforaDCABcommand.
Figure6.DCABCommand
TheDEACcommandclosesasinglebankofmemoryspecifiedbythebankselectsignals.Figure7shows
thetimingsdiagramforaDEACcommand.
Figure7.DEACCommand
DSPDDR2MemoryController 16SPRUEK5A–October2007
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