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Command/Data
Scheduler
Command FIFO
Write FIFO
Read FIFO
Registers
Command
to Memory
Write Data
to Memory
Read Data
from
Memory
Command
Data
EDMA BUS
2.7.1CommandOrderingandScheduling,AdvancedConcept
PeripheralArchitecture
Figure15.DDR2MemoryControllerFIFOBlockDiagram
TheDDR2memorycontrollerperformscommandre-orderingandschedulinginanattempttoachieve
efficienttransferswithmaximumthroughput.Thegoalistomaximizetheutilizationofthedata,address,
andcommandbuseswhilehidingtheoverheadofopeningandclosingDDR2SDRAMrows.Command
re-orderingtakesplacewithinthecommandFIFO.
TheDDR2memorycontrollerexaminesallthecommandsstoredinthecommandFIFOtoschedule
commandstotheexternalmemory.Foreachmaster,theDDR2memorycontrollerreordersthe
commandsbasedonthefollowingrules:
•Selectstheoldestcommand
•Areadcommandisadvancedbeforeanolderwritecommandifthereadistoadifferentblockaddress
(2048bytes)andthereadpriorityisequaltoorgreaterthanthewritepriority.
Note:Mostmastersissuecommandsonasingleprioritylevel.Also,theEDMAtransfercontroller
readandwriteportsareconsidereddifferentmasters,andthus,theaboveruledoesnot
apply.
Thesecondbulletabovemaybeviewedasanexceptiontothefirstbullet.Thismeansthatforan
individualmaster,allofitscommandswillcompletefromoldesttonewest,withtheexceptionthataread
maybeadvancedaheadofanolder,lowerorequalprioritywrite.Followingthisscheduling,eachmaster
mayhaveonecommandreadyforexecution.
SPRUEK5A–October2007DSPDDR2MemoryController23
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