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Contents
Preface...............................................................................................................................6
1Introduction................................................................................................................9
1.1PurposeofthePeripheral.......................................................................................9
1.2Features...........................................................................................................9
1.3FunctionalBlockDiagram.......................................................................................9
1.4IndustryStandard(s)ComplianceStatement...............................................................10
2PeripheralArchitecture..............................................................................................11
2.1ClockControl....................................................................................................11
2.2MemoryMap....................................................................................................11
2.3SignalDescriptions.............................................................................................11
2.4ProtocolDescription(s).........................................................................................13
2.5MemoryWidthandByteAlignment..........................................................................18
2.6AddressMapping...............................................................................................19
2.7DDR2MemoryControllerInterface..........................................................................22
2.8RefreshScheduling............................................................................................25
2.9Self-RefreshMode..............................................................................................26
2.10ResetConsiderations..........................................................................................26
2.11DDR2SDRAMMemoryInitialization.........................................................................27
2.12InterruptSupport................................................................................................28
2.13EDMAEventSupport..........................................................................................28
2.14EmulationConsiderations.....................................................................................28
3UsingtheDDR2MemoryController.............................................................................29
3.1ConnectingtheDDR2MemoryControllertoDDR2SDRAM.............................................29
3.2ConfiguringDDR2MemoryControllerRegisterstoMeetDDR2SDRAMSpecifications.............33
4DDR2MemoryControllerRegisters.............................................................................36
4.1ModuleIDandRevisionRegister(MIDR)...................................................................37
4.2DDR2MemoryControllerStatusRegister(DMCSTAT)...................................................37
4.3SDRAMConfigurationRegister(SDCFG)...................................................................38
4.4SDRAMRefreshControlRegister(SDRFC)................................................................40
4.5SDRAMTiming1Register(SDTIM1)........................................................................41
4.6SDRAMTiming2Register(SDTIM2)........................................................................43
4.7BurstPriorityRegister(BPRIO)...............................................................................44
4.8DDR2MemoryControllerControlRegister(DMCCTL)...................................................45
AppendixARevisionHistory.............................................................................................46
SPRUEK5A–October2007TableofContents3
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