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1.2 System Unit Block Diagram 1 Hardware Overview
PCI Chip Set
North Bridge
ALi M1672 Northbridge with Integrated Graphic Chip
ALi PCI Northbridge Core Logic Processor Support
– Supports Intel Pentium 4 microprocessor family with host bus frequency
can be up to 400MHz
– 64-bit data bus and 32-bit addressing bus
– Optimum buffering architecture design for CPU to memory, AGP and PCI
read/write
– Flexible configuration to support back-to-back read transfer in 1QW or
2QW
– Supports back-to-back write transfer
– Supports synchronous / pseudo asynchronous clock mode between
processor and memory interface with optimized latency
Memory Support
– Supports SDR DRAM PC-100, PC-133
– Supports DDR up to 200, 266MHz
– Supports symmetrical and asymmetrical SDRAM / DDR addressing
– Supports 64, 128, 256, 512Mbit SDRAM / DDR
– Maximum memory size: 3GB
– Supports 6 memory rows with per byte access on each row
– Supports memory shadowing
– x-1-1-1-1-1-1-1 back-to-back page hit
– CAS before RAS and self refresh for SDRAM
– Pipelined SDRAM / DDR cycle control with hidden pre-charge
– Dynamic switching CKE algorithm
– Supports LVTTL / SSTL2 signal level
Advanced Mobile Power Management
– Low power cell design
– Suspend and standby modes
– Internal clock gating on each functional block
– PCIPM (H/W PCI initiated)
– AGP Busy#/Stop# and PCI Clock Run#
– ACPI and DPMS support
High Performance DirectX 7.0 3D Engine
DVD Playback
Satellite A20 Maintenance Manual (960-444) 1-9