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1.2 System Unit Block Diagram 1 Hardware Overview
South Bridge
ALi M1535+ Southbridge
– Provides a high integration bridge between the PCI Bus and Peripheral
Bus (PCI spec. 2.2 Compliant)
– Provides Steerable PCI Interrupts for PCI Device Plug-and-Play
– Enhanced DMA Controller
– Interrupt Controller
– Counter/Timers
– Distributed DMA Supported
– PC/PCI DMA Supported
– Serialized IRQ Supported
– Low Pin Count (LPC) Host Controller
– Plug-and-Play Supported
– Built-in Keyboard Controller
– Supports up to 512 KB ROM Size Decoding PMU Features
– Built-in PCI IDE Controller
– USB Interface
– SMBus Interface
– Super I/O Interface
– Audio System
– Software Modem Interface
– 352-pin (27mm x 27mm) BGA Package
Card Controller:
• YEBISU SS
This gate array has the following functions and components.
– PCI Interface (PCI Rev. 2.2)
– Chipset Interface (Intel serial interrupt)
– CardBus/PC Card Controller (Yenta Ver. 2.2) : 1 slot
– SD memory Card Controller (SDHC Ver. 1.2 enhanced)
– SD I/O card controller (Ver. 1.1)
– SmartCard I/F / Debug port
– External device interface
– Deeper Sleep control interface
Thermo Sensor
• One ADM1032AR is used.
LAN
• One RTL8139DL chip is used
Satellite A20 Maintenance Manual (960-444) 1-11