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Functional Description
MVME2500 Installation and Use (6806800L01H)
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4.2.8 DUART
The chipset provides two universal asynchronous receiver/transmitter (UART), each of which
acts independently of the other. Each UART is clocked by the CCB clock and is compatible with
PC16522D. As a full-duplex interface, it provides a 16-byte FIFO for both transmitter and
receiver mode.
4.2.9 DMA Controller
The DMA controller transfers blocks of data between the various interfaces and functional
blocks of P20x0 that are independent of the e500 cores. The P20x0 DMA controller has three
high-speed DMA channels, all of which capable of complex data movement and advanced
transaction chaining.
4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)
The eTSEC controller of the device communicates to the 10 Mbps, 100 Mbps, and 1 Gbps
Ethernet/IEE 802.3 networks, as well as to devices with generic 8 to 16-bit FIFO ports. The
MVME2500 uses the eTSEC using the RGMII interface.
4.2.11 General Purpose I/O (GPIO)
The P20x0 has a total of sixteen I/O ports. Four of these ports are used alternately used as
external input interrupt. All sixteen ports have open drain capabitilies.
4.2.12 Security Engine (SEC) 3.1
The integrated security engine of the P20x0 is designed to off-load intensive security functions
like key generation and exchange, authenticaion and bulk encryption from the processor core.
It includes eight different execution units where data flows in and out of an EU.
The P20x0 processor provides a Serial Rapid I/O interface. However, this interface is not
utilized by the MVME2500.