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Functional Description
MVME2500 Installation and Use (6806800L01H)
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See Real-Time Clock Battery, on page 77 for more information on the real time clock back-up
battery.
4.4.2 Internal Timer
The processor's internal timer is composed of eight global timers divided into two groups of
four timers each. Each time has four individual configuration registers and they cannot be
cascaded together.
4.4.3 Watchdog Timer
The onboard FPGA provides programmable 16-bit watchdog timers. It has a 1 ms resolution
and generates a board reset when the counter expires. Interrupt is generated to the processor
when this occurs. Default value is 60 seconds.
4.4.4 FPGA Tick Timer
The MVME2500 supports three independent 32-bit timers that are implemented on the FPGA
to provide fully programmable registers for the timers.
4.5 Ethernet Interfaces
The MVME2500 has three eTSEC controllers. Each one supports RGII, GMII, and SGMII interface
to the external PHY. All controllers can only be untilized when using the RGMII interface. Using
the GMII allows only up to two usable controllers.
MVME2500 provides two 10/100/1000 Ethernet interfaces on the front panel and another two
are routed to the RTM through the backplane connector. Due to controller limitations, one
controller is designed to be routed to the front panel or to the RTM. This setting is possible by
using a third party gigabit Ethernet LAN switch with a single enable switch such as PERICOM’s
P13L301D. The routing direction can be configured through the on-board dip switch.
Each Ethernet controller has a single dedicated Broadcom BCM54616S with integrated MAC
and PHY. The registers of the PHY can be accessed through the processor’s two-wire Ethernet
management interface.The front panel RJ45 connector has integrated speed and and activity
status indicator LEDs. Isolation transformers are provided onboard for each port.