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Functional Description
MVME2500 Installation and Use (6806800L01H)
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4.2.13 Common On-Chip Processor (COP)
The COP is the debug interface of the QorIQ P20x0 Processor. It allows a remote computer
system to access and control the internal operation of the processor. The COP interface
connects primarily through the JTAG and has additional status monitoring signals. The COP has
additional features like breakpoints, watch points, register and memory
examination/modification and other standard debugging features.
4.2.14 P20x0 Hardware Configuration Pins
A series of strapping pins are required to initialize the P20x0. These pins are samples during the
assertion of HRESET and return to their assigned function after HRESET is deasserted.
4.3 System Memory
The processor integrated memory controller supports both DDR2 and DDR3 memory devices.
It has one channel and can be configured for up to four memory banks with x8, x16 and x32
devices. Using 4 GB devices allows support of up to 16 GB of memory. ECC is not supported.
The MVME2500 has a total of eight board variants, half of which has soldered 2 GB memory,
while the remaining half has 16 GB memeory. The x8 or 1 Gbit device forms 2 GB and 1 GB
memory capacity. A total of 16 devices for 2 GB and eight devices are used to form 16 GB.
MVME2500 supports ENP1 and ENP2 operating environment. The ENP1 environment uses
Samsung for all variants including the commercial grade devices, while the ENP2 variants use
Micron.
4.4 Timers
There are various timer functions implemented in the MVME2500 platform:
4.4.1 Real Time Clock
This operates on a 3.3 V supply monitoring and battery control function (MAX6364PUT29), a
32.768 KHz clock generator (DS32KHZS) and an RTC with alarm (DS1375T).