Intel CM8063501292204 Computer Hardware User Manual


 
Overview
18 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families
Datasheet Volume One of Two
Static lane numbering reversal support
Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Intel® QuickPath Interconnect (Intel® QPI)
Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
Implements two full width Intel QPI ports
Full width port includes 20 data lanes and 1 clock lane
64 byte cache-lines
Isochronous access support is not available on any CPU model containing two home
agents.
Note: RAS support depends on processor SKU. For example, Workstation SKUs do
not support sparing or tagging, lockstep mode, mirroring mode, channel
mirroring mode within a socket, error containment.
Home snoop based coherency
•4-bit Node ID
46-bit physical addressing support
No Intel QuickPath Interconnect bifurcation support
Differential signaling
Forwarded clocking
Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
All ports run at same operational frequency
Reference Clock is 100 MHz
Slow boot speed initialization at 50 MT/s
Common reference clocking (same clock generator for both sender and receiver)
Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
Polarity Inversion and Lane reversal (Rx side only)
1.2.5 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).
Supports operation at up to 2 Mbps data transfers
Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
Services include CPU thermal and estimated power information, control functions
for power limiting, P-state and T-state control, and access for Machine Check
Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
PECI address determined by SOCKET_ID configuration
Single domain (Domain 0) is supported