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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 55
Datasheet Volume One of Two
Interfaces
While Intel requires reading the accumulated energy data at least once every 16
seconds to ensure functional correctness, a more realistic polling rate recommendation
is once every 100mS for better accuracy. This feature assumes a 150W processor. In
general, as the power capability decreases, so will the minimum polling rate
requirement.
When determining energy changes by subtracting energy values between successive
reads, Intel advocates using the 2’s complement method to account for counter
wraparounds. Alternatively, adding all ‘F’s (‘0xFFFFFFFF’) to a negative result from the
subtraction will accomplish the same goal.
2.5.2.6.25 Power Limit for the VCC Power Plane Write / Read
This feature allows the PECI host to program the power limit over a specified time or
control window for the processor logic supplied by the VCC power plane. This typically
includes all the cores, home agent and last level cache. The processor does not support
power limiting on a per-core basis. Actual power limit values are chosen based on the
external VR (voltage regulator) capabilities. The units for the Power Limit and Control
Time Window are determined as per the Package Power SKU Unit settings described in
Section 2.5.2.6.13.
Since the exact VCC plane power limit value is a function of the platform VR, this
feature is not enabled by default and there are no default values associated with the
power limit value or the control time window. The Power Limit Enable bit in Figure 2-35
should be set to activate this feature. The Clamp Mode bit is also required to be set to
allow the cores to go into power states below what the operating system originally
requested. In general, this feature provides an improved mechanism for VR protection
compared to the input PROCHOT_N signal assertion method. Both power limit enabling
and initialization of power limit values can be done in the same command cycle. Setting
a power limit for the VCC plane enables turbo modes for associated logic. External VR
protection is guaranteed during boot through operation at safe voltage and frequency.
All RAPL parameter values including the power limit value, control time window, clamp
mode and enable bit will have to be specified correctly even if the intent is to change
just one parameter value when programming over PECI.
The usefulness of the VCC power plane RAPL may be somewhat limited if the platform
has a fully compliant external voltage regulator. However, platforms using lower cost
voltage regulators may find this feature useful. The VCC RAPL value is generally
expected to be a static value after initialization and there may not be any use cases for
dynamic control of VCC plane power limit values during run time. BIOS may be ideally
used to read the VR (and associated heat sink) capabilities and program the PCU with
the power limit information during boot. No matter what the method is, Intel
recommends exclusive use of just one entity or interface, PECI for instance, to manage
VCC plane power limiting needs. If PECI is being used to manage VCC plane power
limiting activities, BIOS should lock out all subsequent inband VCC plane power limiting
accesses by setting bit 31 of the PP0_POWER_LIMIT MSR and CSR to ‘1’.
Figure 2-34. Accumulated Energy Read Data
Accumulated Energy Status
Accumulated CPU Energy
0
31