MiTAC 8050D Laptop User Manual


 
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D N/B Maintenance
D N/B Maintenance
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-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D
Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory
controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as
well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP
slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub
architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-M together. Intel®’
I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB
bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O
Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533
MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded
I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O
Link layer to/from INTEL 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data
transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH
adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
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