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8050
8050
D N/B Maintenance
D N/B Maintenance
111
P31
PU3
LTC3734
G
D
S
2
3
1
6
7
8
5
D
S
2
3
1
6
7
8
5
G
+VCC_CORE
24
23
G
D
S
2
3
1
6
7
8
5
G
D
S
2
3
1
6
7
8
5
G
D
S
2
3
1
6
7
8
5
21
22
DVMAIN
+5VS_P
STOP_CPU#
P13
U715
ICH4_M
PR32 0 4
PR104 0
VOS-
PF2
7A/24VDC
PL5
120Z/100M
PL4
120Z/100M
PC12 0.1U
PC13 10U
PU9 PU10
FDS6694 FDS6694
PR740
0.001
PL711
0.68UH
PD718
EC31QS04-TE12L
2N7002
CPU
BANIAS
P3
VID0 PR52 0 13
14
15
17
18
19
PR44
PR40
VID1
VID2
VID3
VID4
VID5
0
0
PR34
PR33
PR31
0
0
0
U713
+5VS_P
PR5 10 29
PR4 10K 31
S1+
S1-
PU12 PU13 PU11
DD_CPU
FDS6694 FDS6694 FDS6694
RUN/SS10
PR61 0
Q19
PWRON_SUSB#
VDD5
PQ5
2N7002
PQ7
2N7002
PR50
1M
PC28
3300P
PU15
P26
LTC3728L
DVMAIN
R251
220K
+2.5VS_DDR
30
2
PR30
100K
PC18
1000P
PR28 576K
PR29
13.3K
3
28100PPC15PR19 13.3K
1
8PR15 56.2k
7
6
PR37
10
10
PR38
PC21
1000P
S1+
S1-
PR43 11
PR17
VOS-
PC11
220P
PR16 1.3M 9
499K
12.7K
To Pin12
+3VS
PR731
2K
PQ8
2N7002
+3V
PR729
249K
PR57
P28
PU703
LTC3728L
0PR59 1M
PQ9
MMBT3904L
12
CLK-
GEN
P11
ICS950810
+3VS
PD4
BAT54C
PR49
100K
PQ10
MMBT3904L
U712
+VCC_PWRGD
G
28
DS
2
1
3
R831
10K
+3V
PR58
4.12K
PR60
43.2K
R821
00
PR56
TO
From Left
8.3 No Display(5)
CPU Core does not exist .
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Confidential Document