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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
29
SIFACL Control for Pseudo-DMA Operation
Pseudo-DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACL
register control of pseudo-DMA operation is shown in Figure 3.
Motorola Mode
Internal
Signals
Host
Interface
SYSTEM_INTERRUPT
(SIFSTS Register)
DMA
Request
DMA
Grant
DMADIR
SIFACL Register
SWDDIR SWHRQ PSDMAEN SINTEN
SWHLDA
M
U
X
M
U
X
M
U
X
SINTR/SIRQ
SHRQ/SBRQ
SHLDA/SBGR
SDDIR
Figure 3. Pseudo-DMA Logic Related to SIFACL Bits