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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
48
PARAMETER MEASUREMENT INFORMATION
83
81
82
80
79
MBCLK1
MBCLK2
MBEN
MDDIR
MAL
MBIAEN
MBRQ
MBGR
80
79
80
79
80
79
Figure 14. Memory Bus Timing: TMS380C26 Resumes Control of Bus (continued)