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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
44
PARAMETER MEASUREMENT INFORMATION
memory bus timing: TMS380C26 releases control of bus
t
M
is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)
NO. PARAMETER MIN MAX UNIT
74 Hold time of MIF output after MBCLK1 rising edge, bus release 0.5t
M
– 13 ns
74a Hold time of MBEN valid after MBCLK1 rising edge, bus release t
M
– 13 ns
75 Delay time from MBCLK1 high to MIF output high impedance, bus release 0.5t
M
ns
75a Delay time from MBCLK1 high to MBEN output high impedance, bus release t
M
ns
76 Setup time of MBRQ low before MBCLK1 falling edge, bus release 24 ns
77 Hold time of MBRQ low after MBCLK1 low, bus release 0 ns
78 Setup time of MBGR low before MBCLK1 rising edge, bus release 29 ns
75
74
75
74
75
74
75
74
75
74
75
74
MBCLK1
MAX0,
MAX2,
MROMEN
MAXPH,
MAXPL,
MADH0–MADH7,
MADL0–MADL7
MRAS
MCAS
MW
MOE
Figure 11. Memory Bus Timing: TMS380C26 Releases Control of Bus