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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
35
PARAMETER MEASUREMENT INFORMATION
S8/SHALT
SRESET
MBCLK2
MBCLK1
OSCIN
SBCLK
V
DD
288
289
119
110
109
110
108
107
106
106
100
Minimun V
DD
High Level
104
105
103
102
101
117
118
111
NOTE A: In order to represent the information on one figure, non-actual phase and timebase characteristics are shown. Please refer to specified
parameters for precise information.
Figure 6. Power Up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET Timing