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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
53
PARAMETER MEASUREMENT INFORMATION
XMATCH and XFAIL timing
t
M
is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)
NO. PARAMETER MIN MAX UNIT
127 Delay from status bit 7 high to XMATCH and XFAIL recognized 7t
M
ns
128 Pulse duration of XMATCH or XFAIL high 50 ns
XFAIL
XMATCH,
MADH7
128
127
Status
Bit 7
Figure 18. XMATCH and XFAIL Timing