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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
71
PARAMETER MEASUREMENT INFORMATION
80x8x mode DMA write timing
NO. PARAMETER MIN MAX UNIT
208a
Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition
on that cycle
15 ns
208b Hold of asynchronous signal SRDY after SBCLK low to guarantee recognition on that cycle 15 ns
212 Delay from SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid 25 ns
215 Pulse duration, SALE and SXAL high t
c(SCK)
–25 ns
216 Delay from SBCLK high to SALE or SXAL high 25 ns
216a Hold of SALE or SXAL low after SWR high t
w(SCKL)
–15 ns
217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns
218 Hold of address valid after SALE, SXAL low t
w(SCKH)
–15 ns
219 Delay from SBCLK low in T2 cycle to output data and parity valid 39 ns
221 Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SWR high t
c(SCK)
–15 ns
223W Delay from SBCLK low to SWR high 25 ns
225W Delay from SBCLK high in T4 cycle to SDBEN high 25 ns
225WH Hold of SDBEN low after SWR, SUDS, and SLDS high t
w(SCKL)
–25 ns
227W Delay from SBCLK low in T2 cycle to SWR low 31 ns
232 Pulse duration, SWR low 2t
c(SCK)
–30 ns
233
Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL
no longer high
t
w(SCKL)
–15 ns
237W Delay from SBCLK high in T1 cycle to SDBEN low 25 ns