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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
84
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
PARAMETER MEASUREMENT INFORMATION
SALE
SDBEN
(see Note A)
SDDIR
SDTACK
(see Notes B and C)
SADL0–SADH7,
SADH0–SADL7,
SPH, SPL
SXAL
SRNW
SUDS,
SLDS
SAS
(see Note A)
SBCLK
HI-ZData InAddress
S7S6S5S4S3S2S1
T1T4T3T2T1TXT4
207a
207b
225R
212
233
233
217
222
215
(High)
223R
216
TWAIT
V
233a
217
206
208a
208b
214
239
216
215
218
210
209
209
216a
229
218
239
237R
247
†
Extended Address
212
205
†
If parameter 208a is not met, then valid data must be present before SDTACK
goes low.
NOTES: A. Motorola-style bus slaves hold SDTACK
active until the bus master deasserts SAS.
B. All V
SS
pins should be routed to minimize inductance to system ground.
C. On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN
becomes no longer active.
Figure 41. 68xxx Mode DMA Read Timing