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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
36
PARAMETER MEASUREMENT INFORMATION
memory bus timing: clocks, MAL
, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS
t
M
is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)
NO. PARAMETER MIN MAX UNIT
1 Period of MBCLK1 and MBCLK2 4t
M
ns
2 Pulse duration of clock high 2t
M
–9 ns
3 Pulse duration of clock low 2t
M
–9 ns
4 Hold time of MBCLK2 low after MBCLK1 high t
M
–9 ns
5 Hold time of MBCLK1 high after MBCLK2 high t
M
–9 ns
6 Hold time of MBCLK2 high after MBCLK1 low t
M
–9 ns
7 Hold time of MBCLK1 low after MBCLK2 low t
M
–9 ns
8 Setup time of address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high t
M
–9 ns
9 Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no longer high t
M
–14 ns
10 Setup time of address on MADH0–MADH7 before MBCLK1 no longer high t
M
–14 ns
11 Setup time of MAL high before MBCLK1 no longer high t
M
–13 ns
12 Setup time of address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low 0.5t
M
–9 ns
13
Setup time of column address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no
longer low
0.5t
M
–9 ns
14 Setup time of status on MADH0–MADH7 before MBCLK1 no longer low 0.5t
M
–9 ns
120 Setup time of NMI valid before MBCLK1 low 30 ns
121 Hold time of NMI valid after MBCLK1 low 0 ns
126 Delay time from MBCLK1 no longer low to MRESET valid 0 20 ns
129 Hold time of column address/status after MBCLK1 no longer low. t
M
–7 ns