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40 VM4016 Programming
The commands for the SCPI commands INP:MASK are received by the control (U1) and data
(U4) buffers and routed to the control FPGA (U3). The mask register circuitry is contained
internally in the control FPGA. This register will be loaded so that Channels 3 through 16 are
disabled or masked out.
The command for the SCPI command INP:POL is received by the control (U1) and data (U4)
buffers and routed to the control FPGA (U3). Channel 1 has been programmed this to NORM so
that the debounce and mask circuitry will treat as an active high. Channel 2 has been programmed
as INV, causing the debounce and mask circuitry to treat Channel 2 as an active low.
The command and data for the SCPI command INP:OFFS are received by the control (U1) and
data (U4) buffers and routed to the control FPGA (U3). The control FPGA will convert the
parallel data for the DAC (U8) into a serial data stream. This data (DACDATA) is synched to the
10 MHz gated clock (DACCLK) and loaded into the DAC when the (DACLOAD) signal goes
high. The DAC output (TRIGLEV#) where # is equal to the Channel number. The DAC will
output TRIGLEV1 for the comparator at U13A and TRIGLEV2 for the comparator at U13B.
The commands for the SCPI command OUTP:POL:EXT:INT are received by the control (U1)
and data (U4) buffers and routed to the control FPGA (U3). U3 uses this command to determine
whether the external interrupt signal should be an active high or an active low. This has been
programmed to NORM so as to cause U3 to output an active high EXTIRQ signal to the front
panel connector when an interrupt occurs. This signal will be a pulse 500 ns wide.
The output of the differential amplifier U17A (BUFCH1) is voltage divided by 4. Since the gain
of U17A is 1.0, this makes BUFCH1 1.250 V when -CH1 reaches +5.0 V. BUFCH1 is compared
with the output of U8 (TRIGLEV1) by comparator U13A. When BUFCH1 is greater than
TRIGLEV1 the output of U13A (COMPCH1) goes low. COMPCH1 is routed to the debounce
circuitry inside U3.
The output of the differential amplifier U17B (BUFCH2) is voltage divided by 4. Since the gain
of U17B is 1.0 this makes BUFCH2 1.250 V when -CH2 reaches +5.0 V. BUFCH2 is compared
with the output of U8 (TRIGLEV2) by comparator U13B. When BUFCH2 is less than
TRIGLEV2 the output of U13B (COMPCH2) goes high. COMPCH2 is routed to the debounce
circuitry inside U3. Note that the only difference in the way these two circuits are working is the
output of the comparator U13B is inverted from the output of U13A. This inversion will allow us
to determine if an under-voltage has occurred. Assume that -CH2 has fallen below +4.75 V. The
output of U13B is now high.
The debounce circuitry will count down for 750 µs before clocking through COMPCH2. When
the 750
µ
s time limit has expired, U3 clocks COMPCH2 into the mask register. The mask register
will AND COMPCH2 with the mask value (0003). The mask register passes COMPCH2 to a 16
input OR’ing function that determines which channel was first to cross its threshold, in this case
COMPCH2. The output of this OR’ing then latches into the “First Latch Register”. This signal,
arbitrarily named FIRSTLATCHED, clocks a series of internal latches that will stretch the pulse
to 500 ns. This pulse drives the base of Q33 low causing Q33 to shut off and the pull-up resistor
provides a high on the front panel connector signal EXTIRQ. When an interrupt condition is
detected by U3 a VXI IRQ* is generated to the VMIP bus.