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42 VM4016 Programming
The VM4016 module supports direct register access for very high-speed data retrieval. The
register map is as specified in Table 3-1.
In order to access the raw data using register access, the register at offset 0x20 must be read. Each
bit in this register corresponds to the state of the 16 channel inputs (unmasked and non-inverted).
Bit 1 corresponds to Channel 1, Bit 2 corresponds to Channel 2 and so on. This information can
also be accessed using the Word Serial FETC:RAW? query.
In order to access the conditioned data using register access, the register at offset 0x28 must be
read. Each bit in this register corresponds to the state of the 16 channel inputs (masked and
inverted). Bit 1 corresponds to Channel 1, Bit 2 corresponds to Channel 2 and so on. This
information can also be accessed using the Word Serial FETC:COND? query.
In order to access the first latched information using register access, the register at offset 0x30
must be read. Each bit in this register corresponds to the state of the 16 channel inputs. Bit 1
corresponds to Channel 1, Bit 2 corresponds to Channel 2 and so on. This information can also be
accessed using the Word Serial FETC:LATC? query.
For example:
a) if a value of 0x8000 is read from the first latched register, then it means that Channel 16’s
input has caused a latching.
b) if a value of 0xF000 is read from the first latched register, then it means that Channels 13
through 16 have caused a latching.
The Interrupt Enable register is a write-only register on which write operations take effect only in
the Pseudo mode. In order to enable backplane interrupting, any non-zero value must be written
to this register at offset 0x38. Writing a zero to this register will disable any backplane
interrupting. It must be noted that in non-pseudo mode, any writes to this register will take no
effect. Backplane interrupting can also be enabled/disabled using the Word Serial
INHOUSE:REG_ENABLE command.