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VM4016 Theory of Operation 87
SECTION 5
THEORY OF OPERATION
INTRODUCTION
The VM4016 is a high-performance Analog Comparator module with 16 input channels per
VMIP daughter module. Each input channel consists of a differential amplifier with a gain of 1 or
0.1 giving an input range of ±10 volts or ±100 volts. Each input is compared against a reference
voltage derived from an independent 8-bit DAC. The VM4016 has a resolution of 78 mV.
Each input signal is digitally debounced for a programmed time ranging from approximately 10
µ
s
to 0.5 s. This prevents input signal noise from causing undesired interrupts. After debounce, the
signal may be programatically inverted to select the input transition edge of interest (rising or
falling edge) and masked to prevent unused channels from causing interrupts.
All the masked inputs are OR’ed together to produce a single interrupt signal. This interrupt
signal is used to generate a VXIbus interrupt as well as the front panel interrupt outputs. Special
logic will latch the first input to cross its threshold, into the First Latched Register. This records
the originating input. The First Latched Register can be cleared by querying the Latched Register
contents using the word serial command FETCh:LATched?, or by querying the data via Pseudo
Register Access with the INHOUSE:CLEAR_LATCH set to 1 or ON.
The state of each channel’s debounced input and the inverted and masked status may be read
directly in the user-defined area of the VXIbus registers, as can the First Latched register. This
information may also be retrieved using the message-based word serial interface.
All channels on the VM4016 are identical in functionality, therefore, descriptions in this theory of
operation will pertain to Channel 1 (CH1) only.