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VXI Technology, Inc.
90 VM4016 Theory of Operation
SIGNAL COMPARISON
Signal comparison between the input signal and a user-defined reference voltage is accomplished
by a differential amplifier, an 8-bit Digital to Analog Converter or DAC and a voltage comparator
(see Figure 5-2). The DAC, U8, is loaded by the control FPGA, U3, and provides the reference
voltage TRIGLEV1.
DACDATA
DACLOAD#
DACCLK
TRIGLEV1
U8
DAC
CONTROL
FPGA
+
-
4. 7K
470K
1K
COMPCH1
4. 7K
VCC
BUFCH1
(FROM FRONT
PANEL CONNECTOR)
U13A
U3
+
-
10pf
2K
6K
100K
10K
100K
100K
+CH1
-CH1
U17A
K9
100K
10K
K9
Data 0-15
Address
0-5, 29
VMIP BUS
Data
CONTROL
CONTROL
BUFFER
DATA
BUFFER
U1
U4
DOE*
FIGURE 5-2: SIGNAL COMPARISON
The command to specify the reference voltage is received in the data and command buffers and
subsequently transferred to the control FPGA at U3. U3 then converts the parallel data to an 8-bit
serial data word DACDATA and synchs the output of this word to the 10 MHz gated clock
DACCLK. Signal DACLOAD1, for Channel 1, goes high providing the control necessary to shift
the serial data into DAC 1. The output TRIGLEV1 of the U8, is used by the comparator U13A as
the reference.