Filter
Top Products
The FIB maintains a copy of the forwarding information contained in the IP routing table based on the
next−hop address. The routing table is updated if routing or topology changes are detected in the network.
Those changes are then forwarded to the FIB, and the next−hop information is recomputed based on those
changes.
Cisco Express Forwarding ASIC
The CEF ASIC and Distributed Cisco Express Forwarding (dCEF) ASIC are Cisco’s newest ASICs; the
company uses them in high−end devices. These are the most functional and efficient ASICs in Cisco’s
product line, including the internal route processors.
The CEF ASIC is used to ensure that all packets have equal access to the switch’s internal memory. It
performs lookups via the CEF ASIC (CEFA) search engine. CEFA uses a round−robin approach, giving fair
access to data traffic on each port as well as cycling data between ports and processing requests as needed.
The CEFA search engine is used to make IP prefix−based switching decisions using an adjacency table. The
CEFA operates at Layer 2 and Layer 3 and uses Address Resolution Protocol (ARP) to resolve next−hop
adjacencies at Layer 2. (A network interface is said to be adjacent if it can be reached in a single hop.) CEFA
looks at the first 64 bytes of an incoming frame, obtains information such as the destination for the frame, and
then uses information contained in the switch’s Content Addressable Memory (CAM) table to rewrite the
relevant source Media Access Control (MAC) address, destination MAC address, or destination network
address to the frame’s or packet’s header.
Because of the efficiency and speed of the CEF ASIC, this ASIC makes more processing available for other
Layer 3 services performed within the main processor, such as queuing, higher encryption levels, and
higher−level decryption.
When using process switching, the RIB and FIB have almost identical data structures. In fast switching,
however, the FIB remains in the Random Access Memory (RAM), and the forwarding is done by the CPU
rather than an ASIC. This process is slower than having ASICs handle the task.
Note Autonomous switching and silicon switching are used on the AGS, AGS+, and 7000 routers. The FIB
has its own separate memory, and the bus controller on an AGS(+) or a Silicon Switch Processor on the
Cisco 7000 series handles the forwarding process. The FIB is on the same board as the forwarding
engine. FIB memory is quite small, so if a particular route or destination address has not been learned or
recently used, cache misses can occur. Cache misses take place when the FIB is invalidated and must be
rebuilt from the knowledge gained by the RIB.
Optimum switching uses both an FIB and RIB. The Route Switch Processor (RSP) card uses them but also
has its own separate physical memory allotted for these processes. With this type of switching, one processor
and one memory set handle the path determination and forwarding.
Distributed switching (either in the CEF ASIC or NetFlow routing) uses only one RIB but copies the FIB to
multiple Versatile Interface Processor (VIP) cards. Each VIP card runs a separate instance of the forwarding
process. The VIP cards have large memories; as a result, in a CEF ASIC the FIB and RIB have a one−to−one
correspondence with each other, so there are no cache misses. Only the first packet to a destination goes
through the RIB to be resolved to a destination. Subsequent packets relating to the same data flow are
forwarded the same as the first packet.
Cisco switches such as the Catalyst 5000 family use distributed Layer 3 switching. This type of switching
uses only one route−determination engine. Although this is a Layer 2 switch, the physical chassis can contain
a separate module such as an RSM, RSFC, or (in the 6000 series) an MSM. Routing can also be handled with
one of the processes described earlier in an external route processor known as an external router. A Cisco
115