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NOTE: x4 and x8 DRAM based DIMMs can be mixed depending on RAS features. However, all
guidelines for specific RAS features must be followed. x4 DRAM based DIMMs retain Single Device
Data Correction (SDDC) in either memory optimized (independent channel) or Advanced ECC
modes. x8 DRAM based DIMMs require Advanced ECC mode to gain SDDC.
The following sections provide additional slot population guidelines for each mode.
Advanced ECC (Lockstep)
Advanced ECC mode extends SDDC from x4 DRAM based DIMMs to both x4 and x8 DRAMs. This
protects against single DRAM chip failures during normal operation. To support Advanced ECC mode,
memory modules must be identical in size, speed, and technology.
• Memory sockets A1 and B1 are disabled and do not supported Advanced ECC mode.
• DIMMs installed in memory sockets A2 and A3 must match each other. Similar rule applies for DIMMs
installed in memory sockets B2 and B3.
NOTE: Advanced ECC with mirroring is not supported.
Memory optimized (independent channel) mode
This mode supports SDDC only for memory modules that use x4 device width and does not impose any
specific slot population requirements.
Memory Sparing
NOTE: To use Memory Sparing, all populated channels must have quad-rank DIMMs and Memory
Sparing must be enabled in the System Setup.
In this mode, one rank per channel is reserved as a spare. If persistent correctable errors are detected on
a rank, the data from this rank is copied to the spare rank and the failed rank is disabled.
With Memory Sparing enabled, the system memory available to the operating system is reduced by one
rank per channel. For example, in a dual-processor configuration with six 32 GB quad-rank DIMMs, the
available system memory is: 3/4 (ranks/channel) × 6 (DIMMs) × 32 GB = 144 GB, and not 6 (DIMMs) × 32
GB = 192 GB.
NOTE: Memory sparing does not offer protection against a multi-bit uncorrectable error.
NOTE: Both Advanced ECC/Lockstep and Optimizer modes support Memory Sparing.
Memory Mirroring
Memory Mirroring offers the strongest DIMM reliability mode compared to all other modes, providing
improved uncorrectable multi-bit failure protection. In a mirrored configuration, the total available
system memory is one half of the total installed physical memory. Half of the installed memory is used to
mirror the active DIMMs. In the event of an uncorrectable error, the system will switch over to the
mirrored copy. This ensures SDDC and multi-bit protection.
Memory installation guidelines to support Memory Mirroring:
• Memory channel 1 (memory sockets A1 and B1) is disabled in this mode.
• Memory channels 2 and 3 must be populated.
• Only quad-rank DIMMs are supported.
• DIMMs installed must be identical in size, speed, and technology.
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