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APPENDIX B Bus Operation List
93 MOVW A, @A 3 1 N +2 The following
following instruction
10 0
2 (A) address Data (H byte) 1 0 0
3 (A) +1 address Data (L byte) 1 0 0
E4 MOVW A, #d16 3 1 N +2 Data (L byte) 1 0 0
E5 MOVW SP, #d16 2 N +3 The following
instruction
10 0
E6 MOVW IX, #d16 3 N +4 The following
following instruction
10 0
E7 MOVW EP, #d16
84 DAA 1 1 N +2 The following
following instruction
10 0
94 DAS
02 ROLC A
03 RORC A
70 MOVW A, PS
71 MOVW PS, A
C8 - CF INC Ri 3 1 N +2 The following
following instruction
10 1
D8 - DF DEC Ri 2 Rn address Data 1 0 1
3 Rn address Data 0 1 0
E8 - EF CALLV #n 7 1 N +2 Data of N +2 1 0 0
2 Vector address Vector (H) 1 0 0
3 Vector address +1 Vector (L) 1 0 0
4 SP -1 Return address (L) 0 1 0
5 SP -2 Return address (H) 0 1 0
6 Address divergence
ahead
The following
instruction
10 0
7 Address divergence
ahead +1
The following
following instruction
10 0
Table B-1 Bus Operation List (8/11)
CODE MNEMONIC ~ Cycle Address bus Data bus RD WR RMW