Filter
Top Products
30
CHAPTER 4 INTERRUPT PROCESSING
4.1 Outline of Interrupt Operation
F
2
MC-8FX series interrupts have the following features:
• Four interrupt priority levels
• All maskable features
• Vector jump feature by which the program jumps to address mentioned in the
interrupt vector.
■ Outline of Interrupt Operation
In the F
2
MC-8FX series, interrupts are transferred and processed according to the following procedure:
1. An interrupt source occurs in resources.
2. Refer to interrupt enable bits in resources. If an interrupt is enabled, interrupt requests are issued from
resources to the interrupt controller.
3. As soon as an interrupt request is received, the interrupt controller decides the priorities of the interrupt
requested and then transfers the interrupt level corresponding to the interrupts applicable to the CPU.
4. The CPU compares the interrupt levels requested by the interrupt controller with the IL bit in the
program status register.
5. In the comparison, the CPU checks the contents of the I flag in the same program status register only if
the priority is higher than the current interrupt processing level.
6. In the check in 5., the CPU sets the contents of the IL bit to the requested level only if the I flag is
enabled for interrupts, processes interrupts as soon as the instruction currently being executed is
completed and then transfers control to the interrupt processing routine.
7. The CPU clears the interrupt source caused in 1. using software in the user’s interrupt processing
routine to terminate the processing of interrupts.