Filter
Top Products
250
APPENDIX
− INTERRUPT 9 1 N +2 Data of N +2 1 0 0
2 Vector address Vector (H) 1 0 0
3 Vector address +1 Vector (L) 1 0 0
4 SP -1 Return address (L) 0 1 0
5 SP -2 Return address (H) 0 1 0
6 SP -3 PSL (CCR) 0 1 0
7 SP -4 PSH (RP, DP) 0 1 0
8 Address divergence
ahead
The following
instruction
10 0
9 Address divergence
ahead +1
The following
following instruction
10 0
-: Invalid bus cycle
N: Address where instruction under execution is stored
Note:
The cycle of the instruction might be extended by the immediately preceding instruction by one cycle.
Moreover, cycle of the instruction number might be extended in the access to the IO area.
Table B-1 Bus Operation List (11/11)
CODE MNEMONIC ~ Cycle Address bus Data bus RD WR RMW