Filter
Top Products
B-2 SPARC Enterprise M4000/M5000 Servers Service Manual • August 2009
TABLE B-1 System Features
Features
SPARC Enterprise
M4000 Server
SPARC Enterprise
M5000 Server Notes
Motherboard unit 1 1 The CPU, memory subsystem, and I/O
subsystem are directly connected to
implement data transfer by using a high-
speed broadband switch. Because individual
components, which are connected through
tightly coupled switches, use an even
latency for data transfer, components can be
added to the system to enhance the
processing capability (in proportion to the
number of components added). When a data
error is detected in a CPU, memory access
controller (MAC), or I/O controller (IOC),
the system bus agent corrects the data and
transfers it.
CPU module (2 processor
chips per CPU module)
2 4 The CPU module consists of two CPU chips.
The CPU is a high-performance multicore
processor. It contains an on-chip secondary
cache to minimize memory latency. It
supports the instruction retry function that
enables continuous processing by retrying
instructions when any error is detected. At
least one CPU Module (CPUM) is required
on each XSB.
Memory board (8 DIMMs
per memory board)
4 (32 DIMMs
total)
8 (64 DIMMs
total)
The memory boards use Double Data Rate
(DDR II) type DIMMs. The memory
subsystem supports up to eight-way
memory interleaving for high-speed
memory access. At least one Memory Board
(MEMB) is required on each XSB. The
quantity of Memory Boards on an XSB must
be a power of two (either 1, 2, or 4). If
mixed memory types are required on a
Memory Board, larger DIMMs must be
placed in Bank A first, all DIMMs in a bank
must be of the same type, and each Memory
Board on an XSB must be configured
identically.