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Selftest Failures
82
2x30 ITAG Icache tag selftest
2x33 DCACHE_ALT_WRITE0
2x40 CACHE_IERR Icache parity error
detection selftest
2x44 DCACHE_ALT_READ0
2x50 DCACHE_STORE_QUEUE Dcache store queue
selftest
2x51 DCACHE_STORE_QUEUE Dcache store queue
selftest
FLT extended info D000/F000 D=data,
F=tag
Address in error[0:15]
(even bank errors end in 0)
Address in error[16:31]
(odd bank errors end in 8)
Expected data[0:15]
Expected data[16:31]
Expected data[32:47]
Expected data[48:63]
Actual data[0:15]
Actual data[16:31]
Actual data[32:47]
Actual data[48:63]
2x55 DCACHE_ALT_WRITE1
2x60 DCACHE_ALINE Dcache Address line
selftest
2x61 DCACHE_ALINE Dcache Address line
selftest
FLT extended info same as 2x51
2x62 DCACHE_ALINE Dcache Address line
selftest
FLT extended info D000/F000 D=data
open, F=tag open
Control Address[0:15]
Control Address[16:31]
Test Address[0:15]
Test Address[16:31]
Actual data[0:15]
(expected data is always 0)
Actual data[16:31]
Actual data[32:47]
Actual data[48:63]
Code Name Meaning
2x66 DCACHE_ALT_READ1
2x70 DCACHE_RAM Starting Dcache RAM
selftest
2x7Y DCACHE_RAM Y = forward progress
2x71 DCACHE_RAM_DATA_ERR Dcache RAM date er-
ror
2x72 DCACHE_RAM_TAG_ERR Dcache RAM tag error
2x77 DCACHE_ALT_WRITE2
2x80 DTAG Dcache tag selftest
2x88 DCACHE_ALT_READ20
2x90 CACHE_DERR Dcache error selft-
est
2x99 DCACHE_ALT_WRITE3
2xA0 PM_CACHE_TESTS PM cache selftest
2xAA DCACHE_ALT_READ3
2xA1-2xA2 PM_RAM_TEST PM RAM selftest
2xA3-2xA6 PM_PTR_TEST PM Pointer selftest
2xA7-2xA8 PM_CAM_TEST PM CAM selftest
2xB0 DCACHE_PARITY Dcache parity error
2xB1 DCACHE_EVEN_TAG_PARITY