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6 Chapter 1
Introduction
Utilities board
Core logic
The core logic contains initialization and booting firmware and is
described in the following sections.
Flash memory
The core logic contains a four-MByte electrically erasable programmable
read only memory (EEPROM) storage for Processor-Dependent Code
(PDC). PDC consists of Power-On Self Test (POST) and Open Boot
PROM (OBP). The V2500 server uses these two components plus
additional firmware called spp_pdc that is laid over OBP and interfaces
OBP to HP-UX. Flash memory also contains all diagnostic test, utilities ,
and scripts.
Flash memory is configured as 512-KByte addresses by 32 data bits with
only 32-bit read and write accesses allowed. EEPROM devices are used
for flash memory so that it may be rewritten for field upgrades. It can
also be written when the SPUC is scanned.
Nonvolatile static RAM
The core logic section contains a nonvolatile battery-backed 128-Kbyte
RAM (NVRAM) for storing system log and configuration information.
This RAM is byte addressable and can be accessed even after power
failures.
DUART
A Dual Universal Asynchronous Receiver-Transmitter (DUART)
provides to RS232 serial ports and a single parallel port. One serial port
provides an interface to a terminal used as a local console to analyze
problems, reconfigure the system, and provide other user access.The
parallel port of the DUART drives the LCD. The second RS232 port can
be used for a modem for field service.
RAM
Random access memory (RAM) provides support for the core system
functions. When the system powers up, the processors operate out of this
RAM to run self test and configure the rest of the node. Once the system
is fully configured, the processors execute out of main memory. The RAM
is byte addressable and is 512 KBytes, configured as 128-KByte
addresses by 32 data bits.