Filter
Top Products
56 Chapter 3
Power-On Self Test
POST modules
POST modules
POST executes modules listed below in chronological order:
• Processor Initialization and Selftest—Each processor initializes itself
on power up or reset in parallel with the other processors.
Initialization includes setting values into the internal diagnostic
registers, initializing the instruction and data caches, clearing a
scratch ram area for stack and data storage, and enabling high-
priority machine checks (HPMC), low-priority machine checks
(LPMC), and transfer of control (TOC). Selftest includes instruction
set tests, instruction and data cache RAM tests and TLB RAM tests.
• SCUB Hardware Initialization—POST clears any error state in the
SCUB, initializes the SCUB hardware registers and DUART, and
initializes and optionally tests the SRAM on the SCUB (see
scuba_test_enable).
• Non-volatile Configuration Data Verification—POST verifies the
checksum of all shared data regions in a battery-backed-up SRAM
(NVRAM). POST verifies only the regions it shares with other
modules, such as OBP, and those private to POST. If a region fails, it
is rebuilt using default values.
• Hardware Configuration Determination—POST determines the ASIC
installations status and verifies that each installed ASIC responds to
register accesses. If one does not, it is reported as failing. POST then
configures the system to utilize the maximum amount of installed
hardware based on the V2500 hardware configuration rules.
• Node Hardware (ASIC) Initialization—POST sets up all available
hardware with the proper operating mode(s) enabled. Routing is
configured for the current hardware population.
• Node Main Memory Initialization—POST probes all installed
memory boards for memory installation status. It then enables each
memory board as a 2-, 4-, or 8-board configuration based on V2500
configuration rules. All remaining memory boards are configured to
have the same logical memory population. It then initializes main
memory in parallel, using up to eight processors using initialization
hardware in the memory controllers.