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64 Chapter 3
Power-On Self Test
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Table 17 Processor initialization steps
Table 18 Processor run-time status codes
Step Description
0 Processor internal diagnostic register initialization
1 Processor early data cache initialization.
2 Processor stack SRAM test.(optional)
3 Processor stack SRAM initialization.
4 Processor BIST-based instruction cache initialization.
5 Processor BIST-based data cache initialization
6 Processor internal register final initialization.
7 Processor basic instruction set testing. (optional)
8 Processor basic instruction cache testing. (optional)
9 Processor basic data cache testing. (optional)
a Processor basic TLB testing (optional)
b Processor post-selftest internal register cleanup. (optional)
Status Description
R RUN: Performing system initialization operations.
I IDLE: Processor is in an idle loop, awaiting a command.
M MONARCH: The main POST initialization processor.
H HPMC: processor has detected a high priority machine check
(HPMC).
T TOC: processor has detected a transfer of control (TOC).
S SOFT_RESET: processor has detected a soft RESET.
D DEAD: processor has failed initialization or selftest.