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For more information about call gates, refer to the
http://www.csee.umbc.edu/~plusquel/310/slides/micro_arch4.html Web site.
5.5.2.1.2.3 Translation lookaside buffers
The System x processor includes other caches, in addition to the hardware caches. These caches are called
Translation Lookaside Buffers (TLBs), and they speed up the linear-to-physical address translation. The TLB
is built up as the kernel performs linear-to physical translations. Using the TLB, the kernel can quickly obtain
a physical address corresponding to a linear address, without going through the page tables. Because address
translations obtained from the TLB do not go through the paging access control mechanism, the kernel flushes
the TLB buffer every time a process switch occurs between two regular processes. This process enforces the
access control mechanism implemented by paging.
5.5.2.1.2.4 Address translations in 64-bit mode
All 16-bit and 32-bit address calculations are zero-extended in IA-32e mode to form 64-bit addresses.
Address calculations are first truncated to the effective address size of the current mode (64-bit mode or
compatibility mode), as overridden by any address-size prefix. The result is then zero-extended to the full 64-
bit address width. Because of this, 16-bit and 32-bit applications running in compatibility mode can only
access the low 4 GBs of the 64-bit mode effective addresses. Likewise, a 32-bit address generated in 64-bit
mode can access only the low 4 GB of the 64-bit mode effective-address space.
5.5.2.1.2.5 Paging in EM64T
The 64-bit extensions architecture expands physical address extension (PAE) paging structures to potentially
support mapping a 64-bit linear address to a 52-bit physical address. In the first implementation of the Intel
EM64T, PAE paging structures are extended to support translation of a 48-bit linear address into a 40-bit
physical address.
Prior to activating IA-32e mode, PAE must be enabled by setting CR4.PAE = 1. PAE expands the size of an
individual page-directory entry (PDE) and page-table entry (PTE) from 32 bits to 64 bits to support physical-
address sizes of greater than 32 bits. Attempting to activate IA-32e mode prior to enabling PAE results in a
general-protection exception.
64-bit extensions architecture adds a new table, called the page map level 4 (PML4) table, to the linear-
address translation hierarchy. The PML4 table sits above the page directory pointer (PDP) table in the page-
translation hierarchy. The PML4 contains 512 eight-byte entries, with each entry pointing to a PDP table.
Nine linear-address bits are used to index into the PML4.
PML4 tables are used in page translation only when IA-32e mode is activated. They are not used when
IA-32e mode is disabled, regardless of whether or not PAE is enabled. The existing page-directory pointer
table is expanded by the 64-bit extensions to 512 eight-byte entries from four entries. As a result, nine bits of
the linear address are used to index into a PDP table rather than two bits. The size of both page-directory
entry (PDE) tables and page-table entry (PTE) tables remains 512 eight-byte entries, each indexed by nine
linear-address bits. The total of linear-address index bits into the collection of paging data structures (PML4
+ PDP + PDE + PTE + page offset) defined above is 48. The method for translating the high-order 16 linear-
address bits into a physical address is currently reserved.
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