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The creation and insertion of a new level, the PUD level, immediately below the top-level PGD directory
aims to maintain portability and transparency once all architectures have an active PGD at the top of
hierarchy and an active PTE at the bottom. The PMD and PUD levels are only used in architectures that need
them. These levels are optimized on systems that do not use them.
It is a less intrusive way to update the page tables’ hierarchy, since it can be ignored by systems not using
these levels. This is the same characteristic maintained by the kernel in the previous implementation of three-
level page table architecture.
With this new implementation, architectures that use four-level page tables can have a virtual address space
covering 128 TB of memory, far more than the 512 GB of virtual address space available with the old one.
5.5.2 Memory addressing
The main memory of a computer is a collection of cells that store data and machine instructions. Each cell is
uniquely identified by a number or its memory address.
As part of executing a program, a processor accesses memory to fetch instructions or to fetch and store data.
Addresses used by the program are virtual addresses. The memory management subsystem provides
translation from virtual to real addresses. The translation process, in addition to computing valid memory
locations, also performs access checks to ensure that a process is not attempting an unauthorized access.
Memory addressing is highly dependent on the processor architecture. The memory addressing for System x,
System p, System z, and eServer 326 systems is described in the following sections.
5.5.2.1 System x
SLES provides enhanced handling of user process and kernel virtual address space for Intel x86-compatible
systems (32 bit x86 systems only). Traditionally, 32-bit x86 systems had a fixed 4 GB virtual address space,
which was allocated so the kernel had 1 GB and each user process 3 GB (referred to as the 3-1 split). This
allocation has become restrictive because of the growing physical memory sizes. It is possible to configure a
4-4 split, where each user process and the kernel are allocated 4 GB of virtual address space. There are two
important benefits to this new feature:
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Figure 5-25: New page-table implementation: the four-level page-table
architecture